The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. In addition, metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on the surface of a wafer, is critical to the operation of a semiconductor device. Typically, the “wiring” of an integrated circuit involves etching trenches and “vias” in a planar dielectric (insulator) layer and filling the trenches and vias with a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to the leakage and adhesion problems experienced with the use of gold. Other metallization materials have included Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP. As the size of integrated circuit devices becomes smaller, architectural feature restrictions, such as line isolation and material resistivity, may limit performance of such devices. To meet the demands of small feature devices, the semiconductor industry is migrating to new materials and architectures. For example, the semiconductor industry has been moving to the use of copper for metallization due to the alloying and electromigration problems that are seen with aluminum. In addition, single and dual damascene architectures are being used to enhance electrical isolation of conducting wires. These architectures continue to evolve, and may be used in structures having less than 0.18 micron minimum feature dimensions. Further, to enhance performance speed possible with these new device architectures and smaller device features, lower dielectric constant materials (i.e., k<2.6) are being used to isolate conducting wires. However, such low dielectric constant materials exhibit characteristic porosity which reduces their mechanical strength, making them relatively fragile materials susceptible to shearing and crushing.
Because of the high degree of precision required in the production of integrated circuits, an extremely flat surface is generally needed on at least one side of the semiconductor wafer to optimize the fabrication process, as well as to ensure proper accuracy and performance of the microelectronic structures created on the wafer surface. As the size of copper damascene structures continues to decrease, such as to minimum feature dimensions no greater than 0.18 microns, non-uniformity due to density variations across a die must be minimized. Therefore, between each processing step, it is usually necessary to polish or planarize the surface of the wafer to obtain the flattest surface possible.
Chemical Mechanical Polishing (“CMP”) machines have been developed to polish or planarize semiconductor wafer surfaces to the flat condition desired for integrated circuit components and the like. For examples of conventional CMP processes and machines, see U.S. Pat. No. 4,805,348, issued Feb. 21, 1989 to Arai et al.; U.S. Pat. No. 4,811,522, issued Mar. 14, 1989 to Gill; U.S. Pat. No. 5,099,614, issued Mar. 31, 1992 to Arai et al.; U.S. Pat. No. 5,329,732, issued Jul. 19, 1994 to Karlsrud et al.; U.S. Pat. No. 5,498,196, issued Mar. 12, 1996 to Karlsrud et al.; U.S. Pat. No. 5,498,199, issued Mar. 12, 1996 to Karlsrud et al.; U.S. Pat. No. 5,558,568, issued Sep. 24, 1996 to Talieh et al.; and U.S. Pat. No. 5,584,751, issued Dec. 17, 1996 to Kobayashi et al.
Typically, as illustrated in FIG. 1, a CMP machine 10 includes a wafer carrier 12 configured to hold, rotate, and transport a wafer 14 during the process of polishing or planarizing the wafer. The wafer carrier is rotated to cause relative lateral motion between the polishing surface and the wafer to produce a substantially uniform thickness. In general, the polishing surface includes a horizontal polishing pad 16, the hardness and density of which depend on the material that is to be polished and the degree of precision required in the polishing process. Polishing pad 16 is attached to a platen 18 which rotates, orbits, and/or dithers. During a polishing operation, the wafer is pressed against the polishing surface with a desired amount of “down force” such that the polishing surface exerts a desired amount of pressure against the surface of the wafer. The carrier and the polishing pad are rotated or orbited, typically at different velocities, to cause relative lateral motion between the polishing pad and the wafer to promote uniform polishing.
An abrasive slurry typically is applied to a top surface 20 of the polishing surface through a conduit 22 during polishing of the wafer. The abrasive slurry acts to chemically weaken the molecular bonds at the wafer surface so that the mechanical action of the polishing surface can remove the undesired material from the wafer surface. For example, slurries used for the CMP of a copper-alloy metallized surface typically comprise a solid abrasive and an oxidizing agent. The oxidizing agent acts to oxidize the metallized surface while the solid abrasive mechanically removes the metal oxide, which tends to be “softer” than the metallized surface, from the surface of the wafer.
The kinetic mechanism for the removal of a metallized surface of a wafer includes the formation of a removable surface film containing the metal and the removal of the film by an abrasive or “rubbing” action. The overall rate of removal of the metallized surface from a wafer is characterized by the rate of formation (kf) of the removable surface film and the rate of abrasion (ka) of the film. If the rate of formation is slower than the rate of abrasion, the formation of the surface film is the rate-determining step and removal of the metallized surface can proceed no faster than the formation of the surface film. If the rate of abrasion of the metallized surface is slower than the rate of formation of the surface film, abrasion of the surface film is the rate-determining step and removal of the metallized surface can proceed no faster than the abrasion. The rate of formation (kf) is proportional to the volume and/or concentration of oxidizing agent that is available to the metallized surface for polishing and to the temperature of the system. Thus, if the distribution of polishing solution available to the metallized surface is increased, the rate of formation is increased. Similarly, if the temperature of the system is modified, for example, by suitably increasing or decreasing the temperature of the polishing solution, the rate of formation may be increased. The rate of abrasion (ka) is dependent on various factors, such as, for example, the pressure applied to the metallized surface from the polishing surface, the velocity of the wafer relative to the polishing surface, and the size and shape of the abrasives contained in the polishing solution. If any one or more of these factors is changed, the rate of abrasion will change accordingly.
Typically for CMP using conventional abrasive slurries, the rate of removal of the metallized surface from the wafer at steady state may be characterized by Preston's Law:                RR=k*Pressure*Velocityfor a given polishing solution, where “RR” is the rate of removal of the metallized surface, “Pressure” is the pressure applied to the metallized surface by the polishing surface, “Velocity” is the velocity at which the wafer moves relative to the polishing surface and “k” is a constant. Thus, as illustrated in FIG. 2, if the polishing solution composition and distribution and the velocity remain constant, rate of removal will be approximately proportional to the pressure across a range of pressures.        
CMP may pose challenges when used for planarizing small device structures. For example, for devices having small feature dual damascene structures, CMP may remove large areas of copper residues but also result in the over-removal of small features. In addition, CMP may result in shearing and crushing of low dielectric constant materials. Capping films formed of materials tolerant to the CMP process are often adhered to the surface of low dielectric constant materials to protect such materials. However, the CMP process may cause cracks and loss of adhesion at the interface between the capping material and the low dielectric constant material. Further, abrasive slurries used in CMP may result in scratching of the wafer surface, oxide erosion, dishing and the creation of defects. The latter is particularly problematic for small structures, as a small defect will significantly jeopardize the performance of an even smaller device feature.
In addition, CMP may cause “edge effects” that reduce the die harvest from a wafer. As the wafer is pressed against the polishing pad, the pad deforms around the edge of the wafer, resulting in greater planarization at the wafer edge relative to the rest of the wafer. These edge effects are problematic as the semiconductor industry migrates from 200 mm wafers to 300 mm wafers. With more die around the edge of a, 300 mm wafer, edge effects will result in damage to a proportionately higher number of die of the 300 mm wafer compared to a 200 mm wafer.
To avoid at least some of these disadvantages, CMP may be performed at low down force pressures, that is, the wafer carrier exerts a relatively low down force when pressing the wafer against the polishing pad such that the wafer experiences a “low down force” pressure against the polishing pad. Typically, a “low down force” pressure range includes pressures of from about 0.10 psi to about 3.0 psi, and preferably includes pressures of from about 0.10 psi to about 1.0 psi.
In addition, abrasive-free, or relatively abrasive-free, polishing solutions have been used to planarize metallized surfaces on semiconductor wafers. Such polishing solutions typically have less than 1 wt % of polishing abrasives and are formed of oxidizers, such as hydrogen peroxide, which react with the metallized surface to form a removable surface film. Abrasive-free polishing solutions also are formed of agents that render the removable surface film water-soluble. An example of such a polishing solution is disclosed in U.S. Pat. No. 6,117,775, issued to Kondo et al. on Sep. 12, 2000, which patent is herein incorporated by reference. Polishing solutions having less than 1 wt % polishing abrasives have been shown to reduce scratching, dishing and oxide erosion. For convenience, abrasive-free and relatively abrasive-free polishing solutions, such as those having less than 1 wt % polishing abrasives, shall be collectively referred to herein as “abrasive-free polishing solutions.”
While exhibiting distinct advantages, abrasive-free polishing solutions may fail to provide adequate rate of removal using conventional polishing pads and delivery mechanisms. Referring again to FIG. 1, a conventional polishing apparatus typically includes a polishing pad 16 with a uniform top surface 20 upon which a polishing solution is delivered via a conduit 22. While this conventional design may achieve acceptable rates of removal of the metal surface using an abrasive slurry, because of the chemically-reactive nature of abrasive-free polishing solutions, this conventional design does not provide for uniform distribution of the abrasive-free solution to the contact area between the wafer and the polishing pad. The wafer typically acts like a “squeegee” preventing even distribution of fresh slurry across the wafer. Thus, the rate of formation of the removable surface film is the rate-determining step of the planarization mechanism.
The disadvantage is particularly problematic for CMP processes that require a low down force pressure of the wafer against the polishing pad. The relationship between the rate of removal and pressure applied to the wafer by the polishing pad for conventional CMP apparatus using abrasive-free polishing solutions is illustrated in FIG. 3. As illustrated in FIG. 3, a “critical down force” point, shown as point A, of non-Prestonian behavior exists, below which rates of removal are not satisfactorily proportional to the applied pressure. At low down force pressure ranges, as depicted between pressure P1 and pressure P2, rates of removal are unacceptably low. Accordingly, for devices requiring low down force CMP processing, such as those formed of low dielectric materials, throughput is decreased as a result of the increase in processing time required to remove the metallized surface. In addition, low down force pressures may result in within-die nonuniformity. Further, because the polishing solution is not uniformly distributed over the surface of the wafer, non-uniform planarization results.
A need therefore exists for a process and an apparatus for improving planarization of metallized surfaces of workpieces using abrasive-free polishing solutions. A need further exists for a process and an apparatus for improving planarization of metallized surfaces using abrasive-free polishing solutions wherein the rate-determining step of the metal removal mechanism of the planarization process is the abrasion of the metallized surface. In addition, a need exists for a process and any apparatus for improving the planarization of copper surfaces wherein the rate of removal of copper from a copper surface of the workpiece is approximately proportional to the pressure at which the workpiece contacts the polishing surface, where the pressure is within a low down force pressure range.